This invention relates to the field of error prevention in microprocessor-related circuits and, more particularly, to an error prevention device which controls the microprocessor power supply as well as resetting the microprocessor.
Many so-called "deadman" timer circuits are known in the field of electronics equipment. Generally, they operate on a clock or reset signal which must be received at regular intervals. If the clock or reset signal is not received at the appropriate time, the deadman timer either switches in an alternate piece of equipment or activates some form of failure indicator. In the case of a device which includes a microprocessor, neither of these responses is satisfactory, especially since "failure" is generally not an equipment failure as such, but rather a failure mode in the microprocessor operation. Such a failure mode could be caused by noise or other spurious signal causing the microprocessor to follow the wrong instruction, provide a wrong output signal or to get caught in a loop of the program. It would be desirable to reset the microprocessor to reinitiate the program when such an error has occurred.
The problem of resetting a microprocessor in the event of a program failure mode becomes more difficult in the environment of the present invention. Here the microprocessor is contained in a battery powered device where, in order to conserve power, the microprocessor is operated in two modes: a first high drain, fully operational mode; and a second reduced drain, reduced operational capability mode. To further minimize power drain, the microprocessor's power supply also has two operational modes that correspond to the two power demand modes of the microprocessor. Thus, in order to reinitialize the operation of the microprocessor, it is necessary to switch the power supply to the full output mode as well as to reset the microprocessor. It is also a requirement that such a deadman timer circuit operate in the reduced operational capability mode of the microprocessor.